Former Mixed Signal Verification Intern at Intel Corp
about 3 years ago
Skill set - Typically verification engineers need to know Verilog, SystemVerilog, Electronic Design Automation (EDA) flow for custom and ASIC design. It also includes fundamentals of VLSI and Advanced VLSI design, Computer Architecture and Computer Arithmetic. In my role, I additionally need to know Analog design and tools (Cadence Virtuoso, Synopsys ICC, Synopsys VCS, Synopsys XA) for analog, digital and mixed signal simulation and understanding/writing capability of SystemVerilog/Verilog code along with UVM. It also requires basics of Tcl/Per script and fluency in Linux commands.