Hardware Engineer intern (Master's or PhD level summer internship)

The Hardware Engineer will be involved in designing, simulating, modeling, and testing solutions related to hardware security. Development will be in based primarily in RTL design using VHDL, Verilog, and/or SystemVerilog. Intern will use Cadence Xcelium to functionally verify HDL designs, and Cadence Genus to synthesize them into netlists for either ASIC or FPGA platforms. Data collection and analytics may be performed on secure hardware.

Requirements:

·        Graduate Student working towards degree in Electrical Engineering, Computer Engineering or relevant technical field

·         Minimum 3.5 GPA (Please list your GPA on your resume to be considered)

·         Classroom level experience programming in any of the following languages (VHDL, SystemVerilog, Verilog, Python, SPICE)

·         Basic understanding of circuit theory and design

·         Completed coursework related to electronics

·         US Citizenship with the ability to obtain a security clearance

·         Good communication and problem-solving skills

Desired Qualifications:

·         Experience with FPGA or ASIC development using HDL

·         Design verification using SystemVerilog

·         Experience with Linux

·         Digital, analog, and/or mixed-signal circuit background

·         Experience with hardware testing for functionality or in a testbed

EOE/Minorities/Females/Vet/Disabled