(#6314408003) Intern, Logic Pathfinding Lab Research Scientist – DTCO
What You’ll Learn
- Project Overview: Standard Cell Library Design and SRAM block modeling for Advanced Logic Nodes
- Skills You'll Learn:
- Standard cell design for advanced technologies (MBCFET and beyond)
- Advanced SRAM bitcell, periphery and data block design and SRAM block modeling
What You’ll Do
- Design standard cell library for MBC and 3D stacked devices.
- Create and optimize advanced SRAM bitcell design, periphery circuits, data blocks.
- Evaluate feasibility and trade-offs in Logic and SRAM for different technology options
Location: Onsite at our San Jose office 5 days a week
Reports to: Principal Engineer, Logic Pathfinding Lab
- Design standard cell library for MBC and 3D stacked devices.
- Create and optimize advanced SRAM bitcell design, periphery circuits, data blocks.
- Evaluate feasibility and trade-offs in Logic and SRAM for different technology options
- Collaborate closely with Samsung DTCO engineers
- Collaborate with university or consortia researchers
- Complete other responsibilities as assigned.
What You Bring
- Graduate student enrolled in a Master or PhD program in VLSI technology and design
- Must have at least 1 academic quarter/semester remaining
- Working experience on DTCO including standard cell design and layout synthesis
- Proficient on programming
- Good knowledge of device architecture beyond FinFET
- You’re inclusive, adapting your style to the situation and diverse global norms of our people.
- An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding.
- You’re collaborative, building relationships, humbly offering support and openly welcoming approaches.
- Innovative and creative, you proactively explore new ideas and adapt quickly to change.