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(#6314381003) Intern, Logic Pathfinding Lab Research Scientist – DTCO

What You’ll Learn

 

  • Project Overview: Standard Cell Library Automation for Advanced Logic Nodes
  • Skills You’ll Learn:
    • Standard cell design and automation for advanced technologies (MBCFET and beyond)
    • DTCO automation to expedite advanced technology definition

 

What You’ll Do

 

  • Enable and optimize standard cell automation for MBC and 3D stacked devices.
  • Develop and implement strategies for automation for standard cell library characterization, and LEF extraction for Samsung advanced technologies.
  • Contribute to DTCO automation for Samsung advanced technologies.

 

Location: Onsite at our San Jose headquarters 5 days a week

Reports to: Principal Engineer, Logic Pathfinding Lab

  • Enable and optimize standard cell automation for MBC and 3D stacked devices.
  • Develop and implement strategies for automation for standard cell library characterization, and LEF extraction for Samsung advanced technologies.
  • Contribute to DTCO automation for Samsung advanced technologies.
  • Collaborate closely with Samsung DTCO engineers
  • Collaborate with university or consortia researchers
  • Complete other responsibilities as assigned.

 What You Bring

  • Graduate student enrolled in a Master or PhD program in VLSI technology and design
  • Must have at least 1 academic quarter/semester remaining
  • Working experience on DTCO including standard cell design and layout synthesis
  • Proficient on programming
  • Good knowledge of device architecture beyond FinFET
  • You’re inclusive, adapting your style to the situation and diverse global norms of our people.
  • An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding.
  • You’re collaborative, building relationships, humbly offering support and openly welcoming approaches.
  • Innovative and creative, you proactively explore new ideas and adapt quickly to change.