Digital Design Engineering Intern

SenseICs is looking for engineering students for our SPRING 2025 INTERNSHIP COHORT! Students should be expected to work 15-30 hours a week on site at our Columbus, Ohio office.  Summer 2025 applicants will not be considered until mid November.

The digital designer is expected to have experience/knowledge with circuit design digital flow from Cadence, Synopsys, or other Computer-aided design (CAD) tools and a working knowledge of analog design principles and signal / power integrity. Their principal tasks include:

1. Writing Verilog/VHDL for ASIC or FPGA
2. Working with Cadence or equivalent Digital ASIC Tool Suite (such as Genus, Innovus, Tempus, Voltus)
3. Working with FPGA design suite (such as Vivado in Xilinx)
4. Working with high-level design, simulation, and verification tools
5. Scripting in Python, PERL, or other high level languages
6. Understanding of Linux OS and command-line interface