Analog Design Engineering Intern

SenseICs is looking for engineering students for our SPRING 2025 INTERNSHIP COHORT! Students should be expected to work 15-30 hours a week on site at our Columbus, Ohio office.  Summer 2025 applicants will not be considered until mid November.

An analog design engineering intern is expected to have completed more than half of their major’s coursework for their degree. They should have some experience and knowledge with circuit design at the transistor level in the Cadence environment or other Computer-aided design (CAD) tools from schematic entry to physical layout and parasitic extraction. Their principal tasks include:

1. Designing and stimulating different analog and mixed-signal blocks like bandgap, IDACs, VDACs, analog reference buffers, ADCs, switched capacitor circuits and amplifiers, SRAM, and IO/ESD design
2. Simulating top chip in a mixed-signal environment
3. Documenting designs for reviews and reports
4. Designing a test system and characterizing the fabricated chip design